IEEE 754 and the Four States: The Work of William Kahan and the Unexplored Quaternary Substrate

The Work of William Kahan and the Unexplored Quaternary Substrate

Authors: Kit Moore, with Claude Date: 2026-01-31 Classification: Research / Literature Review / Foundation Document

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ABSTRACT

This paper summarizes the complete known literature on IEEE 754 floating-point special values, focusing on the work of William Kahan, primary architect of the standard. We document the intended purposes of the four hardware-native states (zero, positive infinity, negative infinity, and NaN), their implementation history, and critically identify a gap in the literature: no published work treats these four states as a quaternary computational substrate. This review establishes the foundation for novel work on native quaternary logic using existing floating-point hardware.

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1. HISTORICAL BACKGROUND

1.1 The Problem (Pre-1985)

Before IEEE 754, floating-point arithmetic was chaos:

"Twenty years ago anarchy threatened floating-point arithmetic. Over a dozen commercially significant arithmetics boasted diverse wordsizes, precisions, rounding procedures and over/underflow behaviors." — William Kahan, 1997 Lecture Notes

Each hardware manufacturer implemented floating-point differently:

• Operations like 0/0 caused program crashes
• Division by zero terminated execution
• No portable way to handle edge cases
• Scientific software was non-portable

1.2 The Intel 8087 Origin (1976-1980)

The standard emerged from Intel's need for a floating-point coprocessor:

Kahan's ethical stance:

"I did not bill Intel for consulting hours spent on those aspects of the i8087 design that were transferred to IEEE p754. I had to be sure, not only in appearance and actuality but above all in my own mind, that I was not acting to further the commercial interest of one company over any other."

1.3 Kahan's Personal Contributions

Kahan credits himself specifically for two features:

1. The inexact flag — allows programmers to test if a result was approximated
2. NaN (Not a Number) — the undefined/unrepresentable value

He received the ACM Turing Award in 1989 for this work — the highest honor in computing.

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2. THE FOUR SPECIAL VALUES

2.1 Bit Pattern Representations

IEEE 754 double-precision (64-bit) encoding:

Key insight: All special values share the same exponent pattern (all zeros or all ones), distinguished only by mantissa content.

2.2 Zero (±0)

Bit Pattern: Exponent = 0, Mantissa = 0

Design Purpose:

• Represent the additive identity
• Allow signed zero for limit behavior (approaching from positive vs negative)
• +0 and -0 compare equal but have distinct representations

Behavioral Properties:

+0 == -0        → true
1/+0            → +∞
1/-0            → -∞

2.3 Infinity (±∞)

Bit Pattern: Exponent = all 1s, Mantissa = 0

Design Purpose:

• Represent overflow results
• Allow computation to continue past overflow
• Preserve sign information in limiting cases

Behavioral Properties:

∞ + ∞           → ∞
∞ - ∞           → NaN (indeterminate)
∞ × 0           → NaN (indeterminate)
x / ∞           → 0 (for finite x)
∞ > any_finite  → true

Kahan's Rationale:

"Being able to denote infinity as a specific value is useful because it allows operations to continue past overflow situations."

2.4 NaN (Not a Number)

Bit Pattern: Exponent = all 1s, Mantissa ≠ 0

Two Types:

Design Purpose:

• Represent undefined/unrepresentable results
• Allow error detection at end of computation sequence
• Fill uninitialized memory (sNaN)
• Placeholder for complex objects (sNaN)

Behavioral Properties:

NaN + x         → NaN (propagation)
NaN == NaN      → false (by design!)
NaN != NaN      → true
isnan(NaN)      → true

Critical Design Decision — NaN ≠ NaN:

"The propagation of quiet NaNs through arithmetic operations allows errors to be detected at the end of a sequence of operations without extensive testing during intermediate stages."

This is why NaN != NaN — it ensures NaN never silently equals anything.

2.5 Payload Bits

NaN has 51 available mantissa bits (after the quiet/signaling bit) that are unused by the standard:

"The specification leaves 51 mantissa bits that get ignored when a double is determined to be Not a Number."

This has led to NaN-boxing — using these bits to store other data types (pointers, type tags). Used by:

• LuaJIT
• JavaScriptCore (WebKit)
• SpiderMonkey (Firefox)

Important: NaN-boxing uses NaN as a container, not as a logical state.

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3. KAHAN'S COMPLETE WORKS

3.1 Primary Sources

3.2 The 1988 Lecture Series

CS 279 at UC Berkeley — "The Floating Point Exposé" — 27 recorded lectures:

Most Relevant to This Research:

• Lecture 5-6: Formats, precision, overflow, underflow
• Lecture 7: Gradual underflow
• Lecture 8: IEEE 754/854 standards
• Lecture 21: Exception handling
• Lecture 26: NaNs, tests, models
• Lecture 27: "Is Floating Point Arithmetic a Moral Issue?"

3.3 Later Reflections

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4. INTENDED USE CASES

4.1 Documented Purposes

The literature consistently describes these values as serving:

1. Error Handling: Graceful failure instead of crashes
2. Limit Behavior: Mathematical limits (1/0 → ∞)
3. Indeterminate Results: 0/0, ∞-∞, etc. → NaN
4. Uninitialized Memory Detection: sNaN for debugging
5. Continuation: Allow computation to proceed past edge cases

4.2 Extended Uses (Post-Kahan)

Later implementations added:

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5. THE GAP IN THE LITERATURE

5.1 What Exists

5.2 What Does NOT Exist

No published work treats {0, +∞, -∞, NaN} as four logical states for computation.

Specific gaps:

1. No quaternary logic gates using IEEE 754 special values
2. No algebra defined over {VOID, LIGHT, DARK, WAVE}
3. No state machines using these four states
4. No connection to any symbolic or semantic system
5. No performance analysis vs. emulated multi-valued logic

5.3 The Conceptual Blind Spot

Kahan and all subsequent literature frame these values as:

• Exception handling mechanisms
• Error propagation tools
• Edge case representations

The frame is always: "These handle problems gracefully."

Never: "These are four native computational states."

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6. HARDWARE CAPABILITIES

6.1 Native Detection

Modern FPUs provide single-instruction detection:

6.2 Native Propagation

IEEE 754 mandates propagation rules:

NaN ⊕ anything = NaN       (for any operation ⊕)
∞ + ∞ = ∞
∞ - ∞ = NaN
∞ × 0 = NaN

These are hardware-implemented, not software emulated.

6.3 Native Comparison

+∞ > any_finite             (true)
-∞ < any_finite             (true)
NaN compared to anything    (false, including NaN)

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7. SYNTHESIS: THE QUATERNARY SUBSTRATE

7.1 The Four States

7.2 Properties Inherited from IEEE 754

Detection: Single instruction per state Propagation: WAVE dominates (NaN + x = NaN) Ordering: DARK < VOID < LIGHT, WAVE incomparable Distinction: Hardware-level, not software encoding

7.3 Novel Observation

These four states have existed in every FPU since 1985. They are:

• Hardware-native (not emulated)
• Universally available (every IEEE 754 system)
• Semantically distinct (different bit patterns, different behaviors)
• Computationally closed (operations on states produce states)

No new hardware required.

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8. CONCLUSION

8.1 Summary of Kahan's Contribution

William Kahan designed IEEE 754's special values as robust error handling for "numerically unsophisticated programmers." This was successful — crashes became rare, computation became portable.

8.2 The Unexplored Territory

For 40 years, these four values have been treated as exceptions rather than states. The literature contains:

• Zero discussion of quaternary logic using float special values
• Zero algebra over {0, ±∞, NaN}
• Zero connection to multi-valued logic theory
• Zero performance comparison to emulated systems

8.3 Research Direction

A subsequent paper will present:

1. Quaternary logic gates using IEEE 754 special values
2. Kleene-style three-valued logic as a subset
3. State machine implementation
4. Performance analysis vs. emulated alternatives
5. Connection to K-vector semantic architecture

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REFERENCES

Primary Sources (Kahan)

1. Kahan, W. "Lecture Notes on the Status of IEEE Standard 754 for Binary Floating-Point Arithmetic." UC Berkeley, 1997.
2. Kahan, W. "Why We Needed a Floating-Point Standard." UC Berkeley, ~1997.
3. Kahan, W. "An Interview with the Old Man of Floating-Point." UC Berkeley, ~1998.
4. Kahan, W. "The Floating Point Exposé." CS 279, UC Berkeley, 1988. 27 lectures.
5. Kahan, W. "Mathematics Written in Sand." 1983.
6. Kahan, W. "Infinity for Schoolteachers." UC Berkeley, ~2000.
7. Kahan, W. "A Numerical Analyst Thinks About AI & Deep Learning." UC Berkeley, 2018.

Secondary Sources

1. IEEE Computer Society. "IEEE Standard 754-1985 for Binary Floating-Point Arithmetic." 1985.
2. IEEE Computer Society. "IEEE Standard 754-2008 for Floating-Point Arithmetic." 2008.
3. IEEE Computer Society. "IEEE Standard 754-2019 for Floating-Point Arithmetic." 2019.
4. Goldberg, D. "What Every Computer Scientist Should Know About Floating-Point Arithmetic." ACM Computing Surveys, 1991.

Historical Sources

1. Engineering and Technology History Wiki. "Intel 8087 Math Coprocessor, 1980."
2. Engineering and Technology History Wiki. "IEEE Standard 754 for Binary Floating-Point Arithmetic, 1985."

NaN-Boxing References

1. Gudeman, D. "Representing Type Information in Dynamically Typed Languages." Section 2.6.1, 1993.
2. Zarycki, P. "Why NaN !== NaN in JavaScript (and the IEEE 754 story behind it)." 2025.
3. Cherkaev, A. "The Secret Life of NaN." 2020.

Multi-Valued Logic References

1. Belnap, N. "A Useful Four-Valued Logic." Modern Uses of Multiple-Valued Logic, 1977.
2. Kleene, S.C. "Introduction to Metamathematics." 1952.

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APPENDIX A: Kahan's Complete Document Archive

Available at: https://people.eecs.berkeley.edu/~wkahan/index.htm

Course Notes

• Math 110: Linear Algebra
• Math 221: Matrix Computations
• Math 128 A/B: Numerical Analysis

IEEE 754 Documents

• ieee754status/IEEE754.PDF — Lecture notes
• ieee754status/why-ieee.pdf — Historical motivation
• ieee754status/754story.html — Personal narrative

Technical Papers

• MathSand.pdf — "Mathematics Written in Sand"
• Infinity.pdf — "About Infinity, for Schoolteachers"
• JAVAhurt.pdf — "How Java's Floating-Point Hurts Everyone"
• 7Nov18.pdf — "Numerical Analyst thinks about AI & Deep Learning"

The 1988 Lectures (Arithmazium)

Available at: https://www.arithmazium.org/classroom/wk88_toc.html

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APPENDIX B: Bit Patterns Quick Reference

Double Precision (64-bit)

Sign: 1 bit
Exponent: 11 bits (biased by 1023)
Mantissa: 52 bits (implicit leading 1 for normal numbers)

+0:    0 00000000000 0000000000000000000000000000000000000000000000000000
-0:    1 00000000000 0000000000000000000000000000000000000000000000000000
+∞:    0 11111111111 0000000000000000000000000000000000000000000000000000
-∞:    1 11111111111 0000000000000000000000000000000000000000000000000000
qNaN:  0 11111111111 1000000000000000000000000000000000000000000000000001
sNaN:  0 11111111111 0000000000000000000000000000000000000000000000000001

Single Precision (32-bit)

Sign: 1 bit
Exponent: 8 bits (biased by 127)
Mantissa: 23 bits

+0:    0 00000000 00000000000000000000000
-0:    1 00000000 00000000000000000000000
+∞:    0 11111111 00000000000000000000000
-∞:    1 11111111 00000000000000000000000
qNaN:  0 11111111 10000000000000000000001
sNaN:  0 11111111 00000000000000000000001

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Dai stihó.